Q3 was a strong quarter for DYNANIC.
We showed our technology at Black Hat and at AI Infra Summit 2026 in the United States. In addition, the last quarter of the year brings eight more industry events. The DYNANIC Q4 2026 events calendar covers open hardware, telecom infrastructure, supercomputing, open-source security, and semiconductors. Moreover, it spans the United States, Europe, and Asia. Below you will find the dates, the locations, and the topics we bring to each show.
DYNANIC Q4 2026 events at a glance
- October 12 – 15 – OCP Global Summit, San Jose, United States
- October 13 – 15 – SEMICON West, San Francisco, United States
- October 13 – 15 – Network X, Vienna, Austria
- October 13 – 16 – Korea Electronics Show, Seoul, South Korea
- October 28 – Altera Innovators Day, San Jose, United States
- November 15 – 20 – SC26 Supercomputing, Chicago, United States
- November 18 – 19 – Slush, Helsinki, Finland
- November 18 – 20 – Suricon, Lisbon, Portugal
- December 9 – 11 – SEMICON, Japan, Tokyo, Japan
Open hardware infrastructure at the OCP Global Summit
October 12 – 15, 2026 | San Jose, United States
The OCP Global Summit brings together the operators, hyperscalers, and hardware vendors behind the open data center stack. CTO Lukáš Kekely will be on site for DYNANIC. His focus is software-defined FPGA acceleration in open infrastructure designs. For example, 400G packet processing, telemetry, and security offload all move work away from host CPUs. However, the key point for hardware teams is platform independence. One software platform runs across multiple FPGA vendors and multiple SmartNIC manufacturers. In addition, it keeps full DPDK and rte_flow compatibility.
Ultra Ethernet IP for AI silicon at SEMICON West
October 13 – 15, 2026 | San Francisco, United States
SEMICON West runs in the same week as the OCP Global Summit. As a result, DYNANIC meets both the operators deploying AI infrastructure and the companies building the silicon inside it. VP of Sales Vladimír Reiff will represent the company in San Francisco. His focus is on teams that design their own ASICs for AI training and inference. For these teams, the accelerator core is only one part of the chip.
The networking between accelerators at 400G and beyond has to be designed in as well. Moreover, it has to keep up with a standard that is still evolving. DYNANIC IP includes our Ultra Ethernet implementation. We develop and validate it at line rate on FPGA hardware. Therefore, silicon teams can license a proven networking block instead of starting a new in-house program. The use case is the one we presented at AI Infra Summit: Ultra Ethernet RDMA at 400G for AI clusters.
Carrier network acceleration at Network X
October 13 – 15, 2026 | Vienna, Austria
Network X moves to Vienna this year. It is Europe’s largest event for telecom infrastructure, broadband, and operator networks. CEO Pavol Korček will represent DYNANIC on the ground. The conversation focuses on the platform side of our technology. For instance, 400G user plane acceleration, first N packet classification, hardware-accelerated traffic steering, and service function chaining. All of it is controlled through standard DPDK interfaces. In short, programmable packet processing no longer requires in-house FPGA expertise. Therefore, operators and network equipment vendors no longer need a dedicated FPGA team.
Asian technology market at Korea Electronics Show
October 13 – 16, 2026 | Seoul, South Korea
DYNANIC will be present at the Korea Electronics Show at the COEX center in Seoul. We join as part of the Czech national pavilion organized by CzechTrade. KES covers electronics, artificial intelligence, semiconductors, and advanced ICT. In addition, it connects international vendors with Korean manufacturers, distributors, system integrators, and investors. Our focus at the show is the next-generation FPGA SmartNIC platform. It serves AI infrastructure, cybersecurity, and high-performance networking. Above all, we are looking for partnerships in one of the most advanced technology markets in the world.
Live demo at Altera Innovators Day
October 28, 2026 | San Jose, United States
Altera Innovators Day is a technical event series for developers, system architects, and engineers. They build AI, communications, industrial, and intelligent edge systems on programmable logic. DYNANIC joins as a partner exhibitor. Above all, we bring a live demonstration of our FPGA SmartNIC platform on Altera Agilex silicon. The demo shows what the development workflow looks like in practice. First, pre-built and validated bitstreams are delivered to a standard FPGA card. Then packet classification, filtering, and steering are configured at runtime through DPDK and rte_flow.
Watch the full breakdown of DYNANIC Suricata IDS acceleration:
Nx400G pipelines for AI fabrics at Supercomputing
November 15 – 20, 2026 | Chicago, United States
The second half of the DYNANIC Q4 2026 events schedule starts in Chicago. SC26 is the international conference for high performance computing, networking, storage, and analysis. Therefore, it is the most relevant stage for the bottleneck we work on. HPC and AI clusters now scale past 400G. Monitoring, telemetry, filtering, and securing that traffic becomes an architectural problem. However, CPUs and fixed-function ASICs cannot solve it without latency jitter or packet loss.
DYNANIC will present line-rate Nx400G pipelines for Ultra Ethernet and RoCEv2. Software-configurable FPGAs handle the hardware acceleration. In addition, we bring a live hardware demonstration. It shows interoperability with standard 400G network interface cards from NVIDIA and Broadcom. The supporting data covers deterministic wire-speed processing with zero packet loss. For example, CPU offload allowed one validated production deployment to shrink its monitoring cluster by a factor of five.
Deep tech and investors at Slush
November 18 – 19, 2026 | Helsinki, Finland
Slush is one of Europe’s principal gatherings of founders and investors. CSO Jan Kořenek will attend on behalf of DYNANIC. His topic is the commercial logic behind our architecture. Because the FPGA is reprogrammed through software, deployed hardware gains value over time. Instead of depreciating against the next ASIC generation, it keeps up with the standard. In other words, that is the difference between a hardware refresh cycle and a software update. Investors and partners are tracking the shift toward 400G in telecom, cybersecurity, and AI infrastructure.
Suricata IDS acceleration at Suricon
November 18 – 20, 2026 | Lisbon, Portugal
Suricon is the annual conference of the Suricata community. Therefore, it is the natural venue for our deep packet inspection work. DYNANIC brings the Suricata Turbo demonstration. It runs hardware-accelerated Suricata IDS at 400G on a Silicom ThunderFjord card with an Altera Agilex FPGA. The setup combines static rule offload through rte_flow with dynamic offload through the Suricata bypass API.
Published results show a 70 percent reduction in CPU load on the inspection path. In addition, the hardware footprint is five times smaller. When the NIC flow table fills up, the system falls back to software bypass transparently. Finally, Suricata Turbo is open source and available at github.com/DynaNIC/suricata-turbo.
Semiconductor ecosystem at SEMICON Japan
December 9 – 11, 2026 | Tokyo, Japan
The final stop on the DYNANIC Q4 2026 events calendar is SEMICON Japan in Tokyo. Field Application Engineer Denis Kurka will represent DYNANIC there. SEMICON Japan concentrates the microelectronics supply chain in one place. It gathers device vendors, board manufacturers, system integrators, and research organizations. Our interest here is the layer above the silicon. In particular, a software-defined FPGA platform lets partners deliver programmable 100G to 400G networking products. As a result, they avoid rebuilding FPGA infrastructure for every device generation.
Will you be attending any of these events? Or do you have additional questions? Reach out in advance to schedule a meeting with our team on site.
