A SmartNIC (Smart Network Interface Card – NIC) is a specialized network adapter that offloads certain processing tasks from the host CPU to the NIC itself. These tasks can include things like packet filtering, encryption/decryption, compression, and other functions that are typically performed by software running on the host. By moving these tasks to the SmartNIC, it reduces the load on the host CPU, increases network performance, and significantly improves overall efficiency.
Solution
An FPGA-based SmartNIC (Field-Programmable Gate Array) is a type of SmartNIC that uses an FPGA to perform offloaded tasks. The FPGA allows for flexibility in terms of the specific tasks that can be performed, as well as the ability to easily update or modify the SmartNIC’s functionality as needed.
FPGAs are integrated circuits that can be reprogrammed to perform a variety of different logic functions. This allows the SmartNIC to be configured to perform specific tasks such as running a custom protocol or algorithm that is not supported by traditional NICs, or to accelerate specific workloads.
Experience Unmatched Network Efficiency
How DYNANIC makes SmartNIC from any FPGA-based networking card?
DYNANIC comes with the universal FPGA packet processing pipeline. This pipeline consists of components required for various packet processing in many use-cases. So it enables full utilization of FPGA-technology without prior FPGA knowledge!
This wire-speed capable FPGA pipeline is controlled from the software by standardized and open-source RTE Flow API from DPDK. For example, to set up the FPGA filtration rule, it is only needed to write units of lines of code in C/C++. So simple!
DYNANIC unique features
Technology behind
The technology behind DYNANIC is built on several key foundations, making it an innovative solution for high-performance processing on FPGA-based network cards:
- DYNANIC employs multi-bus technology to achieve Tbps-level throughput in a single processing pipeline, reducing hardware demands while maintaining packet order. This approach effectively utilizes the full potential of FPGA hardware.
- DYNANIC features a suite of optimized IP Cores for time-critical networking tasks like packet parsing, classification, and connection tracking. These cores deliver superior performance and efficiency.
- DYNANIC is backed by a robust framework simplifying deployment across various FPGA cards. This versatility allows customers to easily select their preferred hardware, ensuring adaptability and future-proofing the solution.
Network Packet Parsing and Header Fields Extraction
Network packet parsing is a crucial operation that must precede any kind of further traffic processing like filtering/classification, deep packet inspection, and even basic routing/switching. With network lanes currently operating at hundreds of gigabits per second, and terabit requirements on the horizon, a high-performance packet parser capable of lossless wire-speed processing is required for any kind of SmartNIC application. Apart from high performance, the parser must support an extensive set of various protocols or tunnels which are changing rapidly as networks are constantly evolving.
DYNANIC utilizes a packet parser based on a unique modular architecture. The parser not only has scalable raw parsing throughput from 100 Gbps up to 1 Tbps but more importantly guarantees the wire-speed parsing of even the shortest packets. In order to achieve such a high level of performance, the main feature of our architecture is to fully exploit the massive processing parallelism offered by modern FPGAs and at the same time it still remains very efficient on the used FPGA resources.
Network Packet Classification and Filtration
The packet classification or filtration is another core operation for many network applications. The need to match incoming packets against a specific set of rules or to select and update a specific data record is crucial in systems like IDS/IPS, firewalls, Anti-DDoS solutions, network monitoring probes, routers/switches and many others. High-performance packet classification and filtration becomes a necessity to accommodate currently operating network lanes. Apart from the common high-performance requirements, each application usually defines completely unique parameters for packet identifier matching, data records storage or update, and set of packet editing or forwarding actions.
Therefore, the overall architecture of each classification pipeline is usually unique, although some of the same underlying principles can be reused. DYNANIC utilizes a generic packet classification pipeline to match needs of many specific applications. However, we have technology for rapid development of custom FPGA-based packet classification and filtration engines. Due to the set of highly reusable building blocks, we can prepare in a very short time a brand new packet processing pipeline that is highly optimized to your specific application.
Fast and Efficient Pattern Matching
Pattern matching is a computationally intensive operation used in many network applications. It plays a significant role in cybersecurity applications like IDS/IPS systems, L7 firewalls, etc. For instance, IDS/IPS systems analyze network traffic and match many patterns based on user-defined rules. The rules usually contain hundreds of thousands of strings or regular expressions. Similarly, L7 filtering or load balancing based on URLs requires matching thousands of strings at extremely high speeds.
DYNANIC provides a solution for fast pattern matching for high-speed networks (hundreds of Gbps), even when working with many patterns. The technology enables matching patterns across all positions in input data without reducing throughput. Furthermore, the solution’s performance remains unaffected by the number of patterns, so the target applications can easily scale the number of supporting rules.
DYNANIC leverages efficient on-chip memory utilization to support hundreds of thousands of rules while maintaining high throughput. The key component of the pattern-matching technology is the pre-filter mode, which identifies shortened strings from user-defined regular expressions or strings. These short strings reliably mark packets containing the user-defined rules while significantly boosting processing efficiency.
The pre-filter integrated into SmartNICs naturally reduces the volume of traffic arriving at processor cores and boosts the application speed. This reduction decreases CPU load for applications such as IDS/IPS systems and L7 firewalls and enhances the overall performance of these network solutions.
Customizations!
Just don’t care about FPGA design, it’s our job! If your application requires some kind of specifical FPGA-based offload engine, we can do it for you. Or even if the given packet processing pipeline should be changed or reconfigured somehow, we are here to do it for you.
Typical use-cases with DYNANIC
FPGA-based SmartNICs are used in a wide range of network applications where high-performance, low-latency, and programmability are important. DYNANIC can help with many use-cases:
FPGA-based SmartNICs can be used to offload processing tasks from the CPU to the FPGA, improving network performance and reducing latency. Examples of processing tasks that can be offloaded include packet processing, encryption/decryption, and compression/decompression.
FPGA-based SmartNICs can be used to implement security functions such as firewall, intrusion detection and prevention, and DDoS mitigation. These functions can be implemented in the FPGA for improved performance and reduced latency.
FPGA-based SmartNICs can be used to capture and analyze network traffic in real-time. This can be useful for troubleshooting network issues, detecting anomalies, and identifying performance bottlenecks.
FPGA-based SmartNICs can be used in financial trading applications where low-latency and high-speed data processing are critical for success.
FPGA-based SmartNICs can be used in content delivery networks to accelerate content caching and delivery, improving user experience and reducing server load.
FPGA-based SmartNICs can be used to accelerate virtualized networking functions (NFV) such as virtual switches and routers, improving performance and reducing latency.
FPGA-based SmartNICs can be used in cloud computing environments to accelerate functions such as storage I/O and network virtualization, improving performance and reducing latency.
FPGA-based SmartNICs can be used in video processing applications such as video transcoding and streaming, enabling faster processing and improved video quality.
FPGA-based SmartNICs can be used in scientific computing applications such as high-performance computing and data analytics, enabling faster processing of large datasets.
DYNANIC enables utilization of FPGA technology in many areas. Do you have some specific use-case and you are not sure that it can be handled too? Contact us, we can explore it without any obligation!
