Thanks to its Ultra Fast DMA engine and efficient software layer, DYNANIC solution is tuned for more than 400 Gbps transfers to and from host computer.
This DMA engine uses multi-channel architecture to support the distribution of data among individual CPU cores (also known as Receive Side Scaling or RSS). The data transfer architecture is highly flexible and supports various PCI Express bus configurations up to PCIe Gen4 x32 and Gen5 x16. Moreover, the DMA engine can utilize more than one PCI Express interface to scale the throughput over 100 Gbps and to achieve 200 and 400 Gbps even on the older generations of PCI Express interfaces.
See previous performance demonstration of this Ultra Fast DMA engine
FPGA resource consumption for one endpoint in 100G, two endpoints in 200G and four endpoints in 400G are shown in the table bellow. Each endpoint is configured with 16 individual channels. Percentages are relative to the total available resources on given FPGA:
Finally, this DMA engine is fully controlled by open-source Linux drivers utilizing DPDK standard.
BrnoLogic company (DYNANIC solution creator) provides several FPGA IPs for utilization in commercial projects and same holds for this Ultra Fast DMA engine. It could be provided as an encrypted netlist for given FPGA technology or even in other form. Do not hesitate to contact us at firstname.lastname@example.org for more information.