Outcomes from the FPGA conference

The FPGA Conference Europe is the leading specialist conference for programmable logic devices. So we had to be there too! Sometimes we even had a queue at our stand 😀

Among other things, the conference focuses on user-oriented, practically applicable solutions that FPGA developers can quickly integrate into their everyday work. We attended several lectures, among which we were especially interested in the presentation entitled “Optimizing Your C++ Code to Implement High-Performance and Resource-Efficient Designs Using AMD Vitis™ High-Level Synthesis (HLS) Tool.” The presentation was given by Alain Darte, principal architect for the AMD high-level synthesis tool Vitis HLS. Alain presented recent AMD status in the field of HLS and focused on practical demonstrations. These HLS tools are under development by all major FPGA vendors for rapid prototyping of FPGA-based applications. The idea behind it is to bring closer ordinary software developers to the FPGA technology. And maybe one picture of the presented slide instead of 1000 words:

Yes, it is still not as easy as is often thought. It will always require “understanding the spirit and core principles of the tool” and there is still needed lot of time to “optimize incrementally”. This confirms that going with the solution of highly optimized IP blocks written in the most efficient language designed for FPGA (or better for chips in general) is the right way. Yes, Hardware Description Languages like VHDL or Verilog are highly complex, and not everyone can write them efficiently. That is one of the reason we introduced DYNANIC solution. It helps ordinary software developers to completely get rid of the FPGA development, so they can focus more on other parts of the system.

We are sometimes asked if the 400 Gbps network lines, which are fully supported by DYNANIC, are still a long way before adoption. According to the interest of big telco and data center operators, we do not think so. Take a look at this screen taken at another very interesting presentation “Rising Demand for High-Speed and High Bandwidth Interconnection” given by Joachim Goertz from 3M:

Yes, someone may argue that the price for 400G equipment is higher compared to slower speed, but the trend is clear. And with the growing number of users and the huge demand for increasing the availability and speed of services, the requirements for the transmission capacity of the lines will continue to grow. And of course it has an impact not only on the network interfaces but also on others, such as PCI Express (DYNANIC support even in the latest available PCI Express generation 5), but you can learn more about this from the presentation available here.

And the most important lecture? Of course ours! Lukas, our CTO, gave a perfect presentation on the topic “Challenges of FPGA-Based SmartNICs for 400 Gbps+”. It had quite a large audience and a lot of interest:

Why? Its simple. It’s new, it’s fascinating, but nobody has much experience with 400 Gbps on an FPGA. Completely new problems come with this speed. It is necessary to bring new techniques for FPGA programming. But we know how to do it, so we decided to share. We have a lot to be proud of! Well done Lukas, well done whole DYNANIC team! Now let’s process all those contacts…