DPDK Summit 2026 took place on May 12–13 in Stockholm, Sweden, and DYNANIC was part of the program. Our colleague Pavlina Patova presented original benchmarking work on rte_flow offloading in her presentation entitled: “Beyond Throughput: Exploring the Ambiguities and Limits of rte_flow Offloading.” And this topic matters directly for anyone seeking to standardize hardware offloading across diverse NIC architectures without sacrificing line-rate performance.
The session was built on DYNANIC’s hands-on experience measuring and benchmarking rte_flow offload behavior across NIC platforms. Rather than working through a feature checklist, the talk examined the practical boundaries that appear in real deployments. Specifically, it addressed ambiguities in spec interpretation, edge cases in offload behavior, and what the API does and does not guarantee at line rate.
The full recording is available on the DPDK Summit 2026 livestream:
Complementing the presentation, Pavlina’s slides are available for download. For a detailed analysis of the research, including methodology and hardware-specific behavior of rte_flow on the Silicom N6010 and other platforms from NVidia and Intel, please refer to our previous accompanying technical post.
The talk generated strong discussion from the audience. Questions touched on offload consistency across varios NIC vendors, behavior at rule table saturation, and integration with existing DPDK-based application stacks.
Other interesting sessions
Beyond DYNANIC’s own session, the program included several talks that reflect where the broader DPDK ecosystem is heading.
- Vladimir Medvedkin from Intel examined how GFNI instructions can speed up software-side RSS hash computation. This is relevant for anyone optimizing packet distribution at scale.
- Roland Sipos from CERN showed DPDK deployed in one of the highest-throughput scientific environments in existence. Here, deterministic performance and zero packet loss are hard requirements.
- Dmitry Kozlyuk from Mitigator Global covered running DPDK directly on RISC-V cores embedded in the NIC, applied to Anti-DDoS use cases.
- Harald Bunke from ipoque GmbH addressed throughput, portability, and operational complexity when integrating DPI software into DPDK-based systems.
These presentations highlight a broader trend: as line rates reach new benchmarks, the ecosystem is shifting toward a hybrid architecture. Whether it’s leveraging GFNI for software acceleration or embedding RISC-V and FPGAs directly into the data path, the industry is moving away from CPU-only processing. DPDK’s role has clearly expanded from a simple packet-processing library to a unified framework that orchestrates these diverse hardware capabilities.
Some takeways
DPDK Summit 2026 confirmed that hardware-software co-design is now the baseline for high-performance networking. For DYNANIC and the broader community, the event highlighted some critical areas:
The DPDK ecosystem is converging on a clear set of demands: API support is a baseline, not a guarantee of production readiness.
Q&A from Pavlina’s session made this concrete: engineers need documentation that goes beyond API specifications and addresses how individual hardware targets actually implement rte_flow logic. As the ecosystem expands to accommodate diverse architectures, from RISC-V to FPGA, DPDK must function as a reliable abstraction layer, enabling hardware acceleration that remains transparent to the application layer and portable across a wide range of link speeds, form factors, and offload pipelines. Those include DPI and anti-DDoS.
For DYNANIC, this is precisely where we focus. Our platform is built to close the gap between complex FPGA hardware and the rte_flow API. Not through documentation as an afterthought, but as a core part of the package. Engineers receive implementation guides and production-ready code examples, enabling FPGA acceleration to be deployed with confidence and consistent, predictable behavior across our full hardware portfolio. From adapters targeting 100G to those operating at 400G and beyond.
To discuss your specific deployment context, feel free to contact DYNANIC team directly:
