Why Ultra Ethernet on FPGA matters for AI infrastructure: Insights from Altera Innovators Day 2026
As AI infrastructure evolves, moving data efficiently is becoming just as important as processing it. That was one of the key themes at Altera Innovators Day 2026, where DYNANIC demonstrated Ultra Ethernet running on real FPGA hardware. As a Gold Sponsor, we ran the demo on Silicom’s ThunderFjord SmartNIC. Specifically, the card is built around an Altera Agilex 7 M-series FPGA with two 400G ports and a PCIe Gen5 x16 interface.
Our VP of Sales, Vladimír Reiff, and FAE Grant Morgan spent the day at our table. They talked with visitors about programmable networking, emerging transport standards, and the growing requirements of AI infrastructure.
One message from Altera CEO Raghib Hussain’s opening keynote resonated especially well with our approach. In short, rapidly evolving AI workloads need hardware that combines high performance with the flexibility to adapt as standards change.
For networking, that combination is becoming increasingly important.
Programmable hardware for an ever-changing environment
In Altera’s announcement that day, Hussain described developers who build systems for rapidly evolving workloads, technologies, and standards. In an interview with SiliconANGLE, he also framed the core challenge in one line: “data movement is the biggest problem to be solved.”
Both points apply directly to networking. AI clusters depend on the fabric that connects accelerators as much as on the accelerators themselves. However, the protocols in that fabric are still changing. Hardware that can be reconfigured as standards evolve, without giving up line-rate performance, is what FPGAs have always offered. As a result, the AI era makes that combination more relevant, not less. That is also why we implement Ultra Ethernet on FPGA: the data path can follow the specification as it evolves.
Agilex 27 raises the ceiling
The main announcement was Agilex 2X, a new portfolio of four FPGA and SoC families. Agilex 27, the first family to launch, targets AI infrastructure, terabit networking, and other bandwidth-intensive applications. For high-speed packet processing, three details stand out:
- HyperFlow, a distributed on-chip data network that Altera says moves multiple terabits per second across the FPGA without consuming soft logic or introducing routing congestion.
- Connectivity beyond 400G: hardened IP for 800G and 1.6T Ethernet, configurable transceivers at up to 256 Gbps, and PCIe 6.0 and 7.0.
- Third-generation HyperFlex fabric, with a 1.8X performance-per-watt improvement over Agilex 7, according to Altera.
Taken together, these point to a clear path for packet processing beyond 400G. In today’s high-speed designs, moving traffic between hardened Ethernet ports and the processing logic consumes a significant share of FPGA resources. A dedicated on-chip network frees that logic for the work that actually differentiates a product. Agilex 27 is a roadmap product: Altera expects engineering samples in the second half of 2027, with Quartus Prime support for early access customers starting in mid-November.
Alongside the silicon, Altera introduced QuartusIQ, an AI expert companion for Quartus Prime Pro designed to accelerate the FPGA design flow from design intent through signoff. It is available now in Quartus Prime Pro 26.3. For teams that build on FPGAs, shorter design cycles matter as much as faster silicon.
We are looking forward to leveraging new hardware from Altera!
What visitors asked about Ultra Ethernet on FPGA
The question we heard most often at our table was not about raw throughput. It was about features and direction: which Ultra Ethernet features do you support today, and what comes next?
That shift mirrors the market. Gartner expects inference spending to surpass training spending for the first time in 2026. Dell’Oro Group reports that switch sales for AI back-end networks overtook front-end networks in the second quarter of 2026. As AI moves from building models to running them at scale, attention moves from raw compute to how efficiently the whole system performs – and the network is a large part of that answer.
Ultra Ethernet is the industry’s response on the networking side. The Ultra Ethernet Consortium published Specification 1.0 in June 2025 and Specification 1.1 on October 12, 2026, adding scale-up support, in-network collectives, and programmable congestion management. The transport foundation is maturing, but endpoint behavior is still being refined from one release to the next.
Our answer to the question was direct. Ultra Ethernet framing and datapath run on real hardware today. Retransmission, congestion response, and multipath – core elements of Ultra Ethernet Transport are next on our roadmap.
What comes next for Ultra Ethernet on FPGA
Thank you to the Altera team for hosting Altera Innovators Day and for supporting an open FPGA ecosystem. We also thank Silicom for the platform our demo runs on, which is part of our solution for Silicom FPGA cards. Finally, thank you to Grant Morgan and Vladimír Reiff for engaging with visitors and representing DYNANIC in San Jose. This was our second year at the event, after the 400G AI networking demo we showed with Silicom in 2025.
If you did not get a chance to talk with DYNANIC team in Altera HQs, book a session with our CTO Lukáš Kekely for a detailed walkthrough of the demo and our Ultra Ethernet roadmap.
Sources
- Altera, Altera Announces Agilex 2X, a Complete FPGA & SoC Portfolio Built for the Future of Intelligent Systems, October 28, 2026
- Altera, Altera Launches QuartusIQ, An AI Expert Companion for Quartus Prime Software, October 21, 2026
- SiliconANGLE, Altera unveils Agilex 2X, betting on AI developers to expand programmable computing, October 28, 2026
- Gartner, Gartner Forecasts Worldwide AI-Optimized IaaS Spending to Grow 96% in 2026, August 10, 2026
- Dell’Oro Group, AI Back-End Networks Switch Sales Surpass Front-End Networks for the First Time in 2Q 2026, September 3, 2026
- Ultra Ethernet Consortium, Specification 1.0 release, June 11, 2025, and Specification 1.1 release, October 12, 2026
- Silicom, ThunderFjord FPGA SmartNIC product page
