DYNANIC to demonstrate 400G Ultra Ethernet for AI Infrastructure at SuperComputing 2026 with Altera
One of the first publicly disclosed FPGA-based Ultra Ethernet RDMA implementations
Chicago, United States – 12.11., 2026 – DYNANIC, a provider of high-performance FPGA-based networking solutions, will demonstrate Ultra Ethernet RDMA running at 400 Gbps on an FPGA at SuperComputing 2026 (SC26), held in Chicago. The live demonstration, 400G Ultra Ethernet for AI Infrastructure, runs at Altera booth 2854, November 17 to 19.
Running on the Silicom ThunderFjord FPGA SmartNIC built around the Altera® Agilex® 7 M-series FPGA, DYNANIC’s RDMA module delivers standards-based Ultra Ethernet communication at up to 400 Gbps per card in each direction, with an architecture designed to scale beyond 400 Gbps. DYNANIC is currently testing the module with selected early customers to validate integration, interoperability, and performance under representative AI and HPC workloads.
In large AI training clusters and HPC simulations, compute nodes regularly pause to exchange results and cannot continue until every node has its data. Delayed or dropped traffic leaves powered, cooled compute idle and extends time to solution. RoCEv2 brought RDMA to Ethernet, but at scale it relies on lossless fabrics and Priority Flow Control. Ultra Ethernet adds multipath packet spraying, selective retransmission, and more scalable congestion control, and runs over both lossless and best-effort Ethernet, as outlined in Ultra Ethernet’s Design Principles and Architectural Innovations.
Fixed-function silicon needs a new hardware generation for every revision of the specification. DYNANIC implements the transport in an FPGA-based packet-processing pipeline, so the same card follows the standard as it evolves. For research centers, the transport is also open to observation and tuning.
Key technical specifications
● Throughput: Up to 400 Gbps per card in each direction over PCIe Gen5 x16.
● Operation rate: 10 MIOPS at 4 kB and 20 MIOPS at 2 kB payloads.
● Latency: Nanosecond-range signaling, microsecond-range data transfer.
Live demonstration at SuperComputing 2026
At the Altera booth 2854, one FPGA card simulates two Ultra Ethernet endpoints with live statistics of the communication, and visitors can change parameters such as payload size. Vladimír Reiff, VP of Sales, and Grant Morgan, Field Applications Engineer, will be at the booth, and meetings can be scheduled online.
Executive quotes
“Ultra Ethernet is still evolving, which makes a programmable implementation especially valuable. By placing the transport in an FPGA-based packet-processing pipeline, we can refine its behavior, support future revisions through firmware, and expose the solution through the standard libfabric interface without requiring customers to redesign their applications or develop FPGA expertise. AI infrastructure should not be locked to yesterday’s hardware roadmap. We enable operators to adopt Ultra Ethernet now and keep adapting it after deployment. ,”
said Lukáš Kekely, Chief Technology Officer at DYNANIC.
“Ultra Ethernet is evolving quickly alongside the demands of AI infrastructure,” said Chuck Tato, Head of Vertical Markets, Altera. “DYNANIC’s Ultra Ethernet endpoint on Agilex® 7 FPGAs delivers 400G performance today, with FPGA flexibility to adapt as the specification evolves.”
About DYNANIC
DYNANIC was founded by researchers and engineers with more than two decades of experience in FPGA-based network acceleration. The company develops high-performance and highly adaptable networking solutions that help infrastructure scale, evolve, and maintain predictable performance using a unique 400G+ approach.
DYNANIC simplifies FPGA adoption through ready-to-integrate software interfaces and programmable packet-processing technology, enabling customers to deploy hardware-accelerated networking without the complexity traditionally associated with FPGA development.
For more information, visit dyna-nic.com/our-story.
About Altera
Altera Corporation is a supplier of programmable logic technology, with a portfolio spanning FPGAs, CPLDs, intellectual property, development tools, and acceleration platforms for cloud, network, and edge applications. The Agilex 7 M-series FPGA used in this demonstration provides the transceiver capacity and PCIe Gen5 host interface required for lossless packet processing at 400 GbE.
For more information, visit altera.com.
Related links
Altera Agilex 7 M-series product page: www.altera.com/products/fpga/agilex/7/m-series
DYNANIC solution page for Silicom hardware dyna-nic.com/Silicom
Silicom ThunderFjord product page: www.silicom.dk/product/fpga-smartnic-fb2cdg1agm39d2-fpga-smartnic-fb2cdg1agm39d-2-thunderfjord/
SuperComputing 2026 (SC26), November 15 to 20, McCormick Place, Chicago: sc26.supercomputing.org
SuperComputing 2026 Schedule: https://sc26.conference-program.com/
Media contact
Tomáš Fiala
Online Marketing Specialist
DYNANIC
fiala@dyna-nic.com
