DYNANIC at Big Data & AI Paris 2026
Booth AC14, Village Advanced Computing
September 15 – 16, 2026 | Paris Expo Porte de Versailles
Talk: Wednesday, September 16, 10:20
Hardware-level performance. Software-like adaptability.
One FPGA card, a single 400G port looped back on itself: the card generates the traffic, sends it, receives it and processes both directions at the same time. Ultra Ethernet framing on the wire at line rate, statistics on screen. Then we change what the pipeline does and reload it while you watch.
- Ultra Ethernet framing and datapath at 400G, on a reflex ces FPGA card
- Live traffic and performance statistics
- Pipeline behaviour changed and reloaded in front of you, no hardware swap
- Standard libfabric API and open drivers
What this is and is not:
:a single port in loopback, so the card is talking to itself. It shows framing, line rate in both directions and how fast behaviour can change. It is not a transport test. The pipeline is ready for the delivery mechanisms, retransmission, congestion response and multipath, and those come next.
Proven at line rate, in production
DYNANIC turns standard FPGA cards into production-ready SmartNICs. The platform runs in operator networks today, doing stateful inspection at line rate. That is the same problem an AI fabric poses, and the same engine solves it, deployed through standard software interfaces, with no RTL and no FPGA expertise required on your side.
400G at 64 bytes
Tens of millions of flows
Seven card vendors
Built for AI and HPC cluster fabrics, line-rate security inspection, telecom data planes and high-performance data centre networks. Supported cards include AMD, Altera, Achronix, BittWare, Silicom Denmark, reflex ces and iWave.
Building your own AI silicon?
The endpoint is where Ultra Ethernet gets hard, and it is a memory problem before it is a protocol problem: out-of-order placement, context scale, a congestion loop that never touches the CPU. We are building that endpoint on an adaptable 400G pipeline, to hand over as hardware-validated, ASIC-portable RTL. If you are freezing an I/O die architecture in the next year, this is the right moment to talk, while the requirements can still be yours.
Let’s talk endpoint architecture
Meet us in Paris
Speaking session: Programmable 400G SmartNICs for AI and security, Wednesday, September 16, 10:20 – 10:40.
At the booth: Jan Kořenek, CSO & Co-Founder · Jan Přívara, Senior FPGA Developer
Cannot make it to the booth? Tell us what you are trying to build. You will be talking to the engineers who built it.