September 15 – 17, 2026
DYNANIC at AI Infra Summit 2026
San Jose, Santa Clara Convention Center
Find us at Start Up Zone 1001
Ultra Ethernet at 400G, running today
As training and inference scale across more accelerators, collective operations in AI clusters generate synchronized, burst-heavy traffic that puts the network fabric under increasing pressure.
RoCEv2 helped bring RDMA to Ethernet and enabled its broad adoption. Ultra Ethernet builds on that foundation for a new generation of distributed AI infrastructure, introducing mechanisms such as multipath packet spraying, flexible packet ordering, selective retransmission, and more scalable congestion control.
The result is a transport designed around how large AI workloads actually communicate.
At AI Infra Summit 2026, DYNANIC will demonstrate Ultra Ethernet RDMA operating at up to 400 Gbps per card in each direction, implemented inside a programmable FPGA packet-processing pipeline and exposed through the standard libfabric API.
400 Gbps
20 MIOPS
Full Ultra Ethernet
Watch our product video:
What you will see at Start UpZone 1001 (Level 1)
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Live 400G Ultra Ethernet
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Real-time communication and performance statistics
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Ultra Ethernet transport implemented in a programmable FPGA data path
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Integration through the standard libfabric API
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A working implementation that can evolve through firmware as the specification develops
At Start UpZone 1001, you can discuss topics such as cluster utilization, lossless fabric behavior under collective traffic, Ultra Ethernet adoption paths, and integration through libfabric with:
- Pavol Korček — CEO & Co-Founder
- Lukáš Kekely — CTO & Co-Founder
- Vladimír Reiff — VP of Sales
We also recommend joining the speaking session “Keeping pace with AI protocol evolution: Scaling next-gen infrastructure via software-configurable FPGA pipelines,” presented by Lukáš Kekely, CTO and Co-Founder at DYNANIC. He will show how a software-configurable FPGA pipeline keeps pace with protocols that are still being ratified, including Ultra Ethernet, so that adopting the next revision of a standard does not depend on the next generation of silicon.
Speaking session – Expo Theater 2
Wednesday, September 16 | 11:45am – 12:00pm
Read the technical detail
Prefer the technical detail first? Read how DYNANIC processes multiple packets in a single deterministic pipeline instead of replicating parallel 100G pipelines, and what that means for lossless behavior at 400G. Read:
Beyond pipeline replication — rethinking FPGA packet processing for the 400G era
Ready to evaluate Ultra Ethernet at 400G without waiting for the next silicon generation? Book a meeting with the DYNANIC team at AI Infra Summit 2026.
Cannot make it to the booth? Talk to us directly.
Send us a message and the DYNANIC team will follow up about a live 400G Ultra Ethernet demonstration, technical details, or other options of meeting.